Multi-thread processor selecting threads on different schedule pattern for interrupt processing and normal operation
US8539203B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2009 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Jan 19, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an exemplary aspect, the present invention provides a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a first or second schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread, and an execution pipeline that executes an instruction output from the first selector, wherein when the multi-thread processor is in a first state, the thread scheduler selects the first schedule, and when the multi-thread processor is in a second state, the thread scheduler selects the second schedule.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.