System-on-a-chip (SoC) security using one-time programmable memories
US8539216B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2012 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Oct 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/84
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system-on-a-chip including a first one-time-programmable memory, a second memory, a test interface, an input circuit, and a processor. The input circuit is configured to receive data transmitted from a third memory to the system-on-a-chip. The processor is configured to, while booting up the system-on-a-chip, determine whether a first one-time-programmable memory has been previously programmed. The processor is also configured to (i) in response to the first one-time-programmable memory not having been previously programmed, enable the test interface for debugging of the system-on-a-chip, (ii) based on the first one-time-programmable memory having been previously programmed, disable the test interface, and (iii) subsequent to one of the enabling of the test interface and the disabling of the test interface, load the data from the third memory into the second memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.