Reducing leakage current during low power mode
US8539272B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2010 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Jun 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is disclosed that may include an integrated circuit (IC) with an initialization bus configured to communicate with at least one low power mode latch operating during a initialization mode to set a value into the low power mode latch and configured to respond to the assertion of a low power mode signal by selecting the low power mode latch state to drive at least one logic gate to minimize leakage current during the low power mode. The IC may similarly configure and operate a RAM. A leakage control table may be used during initialization mode and created by other embodiments. The net list of a circuit block including at least part of the configuration block and lower power control latch may be used and/or modified to create a new net list to further minimize leakage current during low power mode. Installation packages and program systems are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.