Memory testing system and method of computing device
US8539289B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 7, 2011 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Feb 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory testing method for testing a memory module of a computing device, an operating voltage of the memory module is adjusted to a first voltage or a second voltage. A predetermined data set is written into the memory module after the operating voltage of the memory module is adjusted, and the written data set is read out from the memory module, to accomplish a data writing and reading process of the memory module. A register value that presents how many memory errors have occurred during the data writing and reading process is acquired from an ECC register of the memory module, to determine whether the memory module is stable during the adjusting of the operating voltage according to the register value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.