Parity generating apparatus and map apparatus for turbo decoding
US8539325B2 · kind B2 · utility
0Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2010 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Nov 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3927
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for generating a parity bit for turbo decoding, and a MAP (Maximum A Posteriori) apparatus are provided. The apparatus for generating a parity bit for turbo decoding includes: a index converter calculating forward and reverse state matrices with respect to a parity bit by maintaining or changing the relationship between the forward and reverse state matrices with respect to information bits and input symbols according to an encoder state; and a parity calculation unit calculating a parity bit by using the forward and reverse state matrices calculated by the parity state matric calculation unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.