Reducing observability of memory elements in circuits
US8539403B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2011 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Aug 23, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus and computer program product for modifying a circuit design. The method comprising: obtaining a design of a circuit, the design comprising at least a first memory element and a second memory element. The method further comprising selecting the second memory element to be a dominant memory element over the first memory element. The method further comprising modifying the design of the circuit by replacing usage of an output signal of the first memory element with usage of an output signal of the dominant memory element in one or more cycles in which values of the output signals of the first memory element and the dominant memory element are equal. Whereby a reduction in observabiltiy of the first memory element in the design is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.