Functional simulation redundancy reduction by state comparison and pruning
US8539404B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2011 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Dec 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems initiate a simulation of an integrated circuit design. The simulation produces data that will exist in latches of the integrated circuit design when a device manufactured according to the integrated circuit design is operating. The methods and systems evaluate same-state latches associated with different portions of the simulation. If two of the same-state latches have the same state, given the same inputs and environmental conditions, the method and systems terminate a first portion of the simulation associated with a first of the same-state latches, but allow a second portion of the simulation associated with a second of the same-state latches to proceed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.