Equivalence checking for retimed electronic circuit designs
US8539406B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jan 31, 2011 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Apr 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and technology for formally verifying a first electronic design with a second electronic design that has been synthesized from the first electronic design, wherein the synthesis process included structural transformation operations, is provide herein. In various implementations, a first design and a second design are received. The second design having been synthesized from the first design, where no structural transformation operations were performed during synthesis of the second design. Additionally, a third design and a structural transformation guidance file are received. The third design having also been synthesized from the first design, but, where structural transformation operations were performed during synthesis of the third design. The structural transformation guidance file specifies what transformations where made during synthesis. Subsequently, a first formal verification process is implemented to verify the equivalence of the first design to the second design using conventional formal verification proofs. A modified second design is then generated, by applying changes to the second design to correspond to the structural transformations detailed in the stru…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.