Frequency optimization using useful skew timing
US8539413B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2010 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Mar 2, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit analysis tool is provided for optimizing circuit clock operating frequency using useful skew timing analysis. The instructions supply clock signal with an optimized operating frequency. A first gate signal input slack time is determined with respect to the clock signal to the first gate. If the first gate signal input has a negative slack time, a delay is added to the first clock signal. A second gate signal input slack time is determined with respect to the clock signal to the second gate. If the second gate signal input slack time is negative, a delay is added to the second clock signal necessary to create a second gate signal input positive slack time. In response to the first and second gate signal input positive slack times, it is determined that the circuit successfully operates at the clock optimized operating frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.