Thread scheduling in chip multithreading processors
US8539491B1 · kind B1 · utility
11Cited by
7References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 26, 2004 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Jul 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5083
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A thread scheduling technique for assigning multiple threads on a single integrated circuit is dependent on the CPIs of the threads. The technique attempts to balance, to the extent possible, the loads among the processing cores by assigning threads of relatively long-latency (low CPIs) with threads of relatively short-latency (high CPIs) to the same processing core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.