Monolithic integration of multiple compound semiconductor FET devices
US8541271B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 6, 2012 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Apr 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/82
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various aspects of the technology provide a dual semiconductor power and/or switching FET device to replace two or more discrete FET devices. Portions of the current may be distributed in parallel to sections of the source and drain fingers to maintain a low current density and reduce the size while increasing the overall current handling capabilities of the dual FET. Application of the gate signal to both ends of gate fingers, for example, using a serpentine arrangement of the gate fingers and gate pads, simplifies layout of the dual FET device. A single integral ohmic metal finger including both source functions and drain functions reduces conductors and contacts for connecting the two devices at a source-drain node. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.