Method for manufacturing a semiconductor device having high-voltage and low-voltage transistors
US8541279B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | Sep 22, 2010 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Feb 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
By covering ends of a field insulating film in a region where a MOS transistor having a relatively thin gate insulating film is formed with a relatively thick gate insulating film, a channel region of the MOS transistor having the relatively thin gate insulating film is set apart from an inversion-preventing diffusion layer formed under the field insulating film so as not to be influenced by film thickness fluctuation of the field insulating film, etching fluctuation of the relatively thick gate insulating film, and impurity concentration fluctuation at both sides of the channel due to the inversion-preventing diffusion layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.