Manufacturing method of thin film transistor array substrate
US8541288B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2013 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Feb 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method for a TFT array substrate includes providing a substrate; defining a plurality of normal alignment regions and a plurality of abnormal alignment regions on the substrate; forming an insulating layer and a transparent conductive layer on the substrate; performing a patterning process to at least one of the insulating layer and the transparent conductive layer to form a plurality of alignment structures in each abnormal alignment region; forming an alignment material layer on the substrate, the alignment material layer having a plurality of first alignment slits formed along the alignment structures in each of the abnormal alignment regions; and performing a rubbing alignment process to form a plurality of second alignment slits on the alignment material layer in each of the normal alignment regions along a alignment direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.