Nonvolatile semiconductor memory device and method for manufacturing the same
US8541830B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2012 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Aug 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.