Integrated circuit memory devices having vertical transistor arrays therein and methods of forming same

US8541832B2 · kind B2 · utility

Assignees

• SAMSUNG ELECTRONICS CO., LTD. · KR
• The Regents of the University of California · US

Inventors

• Ji-Young Kim · Suwon-si, KR
• Kang L. Wang · Santa Monica, US
• Yong-Jik Park · Seojong-myeon, KR
• Jeong-Hee Han · Seojong-myeon, KR
• Augustin J. Hong · White Plains, US

Key dates

• Filing date: Jun 16, 2010
• Grant date: Sep 24, 2013
• Expiry date: Oct 28, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/69

Abstract

An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.