Semiconductor device
US8541846B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 14, 2011 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Nov 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
Abstract
At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion. The transistor in a lower portion which is covered with an insulating layer is subjected to planarization treatment, whereby the gate electrode is exposed and connected to a layer functioning as source and drain electrodes of the transistor in an upper portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.