Semiconductor memory device and power line arrangement method thereof
US8541893B2 · kind B2 · utility
0Cited by
2References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2005 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Dec 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device and a power line arrangement method are disclosed. The semiconductor memory device includes a plurality of pads, each pad including an upper pad and a lower pad arranged below the upper pad, wherein pad power lines are arranged below the lower pads of the plurality of pads in a direction of crossing the pads to interconnect the pads that transmit the same level of electrical power among the plurality of pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.