Interleaved analog to digital converter with reduced number of multipliers for digital equalization
US8542142B2 · kind B2 · utility
9Cited by
13References
9Claims
0Family size
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Key dates
| Filing date | Feb 21, 2013 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Feb 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.