Semiconductor device having a plurality of memory regions and method of testing the same
US8542544B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2010 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Jan 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include, but is not limited to, first and second memory regions, and first to fifth control circuits. The first and second memory regions are mutually exclusive at the same time. The first control circuit performs a first access to the first memory region. The second control circuit performs a second access to the second memory region. The third control circuit controls activation and deactivation of the first and second control circuits based on a first logic received from a plurality of first external terminals. The fourth control circuit switches between the first and second accesses based on at least a second logic received from a second external terminal. The fifth control circuit controls validation and invalidation of the fourth control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.