Managing free packet descriptors in packet-based communications
US8542693B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2008 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Jul 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9073
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network element including a processor with logic for managing packet queues including a queue of free packet descriptors. Upon the transmission of a packet by a host application, the packet descriptor for the transmitted packet is added to the free packet descriptor queue. If the new free packet descriptor resides in on-chip memory, relative to queue manager logic, it is added to the head of the free packet descriptor queue; if the new free packet descriptor resides in external memory, it is added to the tail of the free packet descriptor queue. Upon a packet descriptor being requested to be associated with valid data to be added to an active packet queue, the queue manager logic pops the packet descriptor currently at the head of the free descriptor queue. Packet descriptors in on-chip memory are preferentially used relative to packet descriptors in external memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.