Receiver architecture and methods for demodulating binary phase shift keying signals
US8542779B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 2013 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Jan 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.