Multi-channel sample rate converter
US8542786B2 · kind B2 · utility
2Cited by
8References
8Claims
0Family size
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Key dates
| Filing date | Aug 4, 2010 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Apr 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2218/06
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method of sample rate conversion and clock synchronization for multiple asynchronous input signals using a single processing core. A sample processing clock with a frequency equal to or higher than the input signal clock frequencies is provided. The clock period is divided into a number of time slots corresponding to the input signals. For each valid sample of an input signal, the core performs a first stage processing operation on the sample. Subsequently, for each required sample of an output signal, the core performs a second stage processing operation to generate the output sample.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.