Compact photonic integrated circuit having geometrically arranged active and passive regions
US8542958B2 · kind B2 · utility
1Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2009 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Nov 23, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B6/12011
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
According to this disclosure, embodiments of the present invention include photonic integrated circuits having active and passive geometric regions geometrically arranged to provide for more compact integrated photonic integrated circuits which, in turn, leads to higher chip yields and lower fabrication costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.