Patent · US Active

Data processing system and method for cache replacement using task scheduler

US8544008B2 · kind B2 · utility

0Cited by

6References

7Claims

0Family size

Assignee

NXP B.V. · NL

Inventors

Sainath Karlapalem · Bengaluru, IN
Bijo Thomas · Thiruvalla, IN
Nagaraju Bussa · Kanchinakote, IN

Key dates

Filing date	Dec 5, 2005
Grant date	Sep 24, 2013
Priority date	—
Expiry date	Jul 30, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0862
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A data processing system is provided with at least one processing unit (1) for an interleaved processing of multiple tasks (T1-T3), and a cache (5) associated to the at least one processing unit (1) for caching data for the multiple tasks (T1-T3) to be processed by the at least one processing unit (1). The cache (5) is divided into a plurality of cache lines (6). Each of the cache lines (6) is associated to one of the multiple tasks (T1-T3). Furthermore, a task scheduler (10) is provided for scheduling the multiple tasks (T1-T3) to be processed in an interleaved manner by the at least one processing unit (1). A cache controller (20) is provided for selecting those cache lines (6) in the cache (5), which are to be evicted from the cache (5). This selection is performed based on the task scheduling of the task scheduler (10).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.