Manufacturing method of wafer level chip scale package of image-sensing module
US8546739B2 · kind B2 · utility
5Cited by
2References
15Claims
0Family size
Inventors
Key dates
| Filing date | Aug 13, 2009 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Apr 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8063
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a wafer level chip scale package of an image-sensing module is provided. The method includes providing a wafer having a plurality of die regions, and a plurality of sensing units is formed on a surface of the wafer in each die region. A plurality of lens units is formed on the sensing units, wherein each lens unit includes a lens and an edge wall that are integrally formed. A light-shielding film is also formed on a surface of at least one edge wall of at least one lens units. A dicing process is then performed on the wafer to form a plurality of image sensor chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.