Architecture for high speed serial transmitter
US8547134B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2012 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Jul 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0278
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system provides for a serial transmitter with multiplexing and driving functionality that is combined into a single stage to increase the overall speed of the serial transmitter. The single stage includes a dynamic impedance that is configured in parallel with a multiplexing driver to reduce the input capacitance and set the correct output impedance. The single stage can be implemented as a stacked or cross-coupled XOR logic circuit or a stacked or cross-coupled multiplexer (“mux”) as the multiplexing driver. In an embodiment where a mux is used as the multiplexing driver, a clock can be injected into the mux driver to overcome inter-symbol interference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.