Programmable noise filtering for bias kickback disturbances
US8547169B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2011 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | May 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method are disclosed for reducing the kickback disturbance in an electronic circuit. The system is based on the coupling of a programmable noise filter between bias blocks. In one embodiment the programmable noise filter includes capacitors, resisters and switches and forms a C-R-C circuit structure. By selecting the resistance and capacitance values and the status of the switches, the performance of the programmable noise filter is determined. Also disclosed is a system and method to reduce kickback disturbances comprising N+1 bias blocks, N programmable noise filters, and a bias reference generator, wherein N is equal to or greater than one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.