Charge sharing analog computation circuitry and applications
US8547272B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2011 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Aug 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04R25/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.