PLL, display using the same, and method for timing controller to generate clock using the same
US8547317B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 18, 2011 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Oct 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J2200/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided are a phase-locked loop (PLL) receiving an input clock and generating a clock, a display using the PLL, and a method for a timing controller to generate a clock using the PLL. The display includes a timing controller configured to generate a first clock using a PLL, insert the first clock into data, and transmit the data into which the first clock is inserted, transmission lines configured to transfer the data into which the first clock is inserted, and data-driver integrated circuits (ICs) configured to receive the data into which the first clock is inserted, separate the first clock from the data, and drive data lines of a liquid crystal panel on the basis of the first clock and the data. The PLL includes a phase detector configured to generate a DC error corresponding to a phase difference between an input clock and the first clock, a plurality of voltage-controlled oscillators (VCOs), a VCO selector configured to select a VCO having a frequency operating range, which is a range from the highest oscillation frequency of the VCO to the lowest oscillation frequency, including a frequency of the first clock from among the plurality of VCOs with reference to the DC error, a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.