Stacked memory device and method thereof
US8547719B2 · kind B2 · utility
2Cited by
7References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2009 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Sep 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information, and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.