Memory cell, methods of manufacturing memory cell, and memory device having the same
US8547763B2 · kind B2 · utility
8Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2011 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Dec 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a selection transistor on a substrate and an antifuse on the substrate. The selection transistor includes a first gate connected to a read word line, a first gate insulation layer that insulates the first gate from the substrate, a first source region connected to a bit line, and a first drain region, an impurity concentration of the first drain region being lower than an impurity concentration of the first source region. The antifuse includes a first electrode connected to a program word line and a second electrode connected to the selection transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.