Patent · US Active

Energy efficient power distribution for 3D integrated circuit stack

US8547769B2 · kind B2 · utility

65Cited by

3References

13Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Ruchir Saraswat · Swindon, GB
Andre Schaefer · Hersbruck, DE
Supriyanto Supriyanto · Braunschweig, DE

Key dates

Filing date	Mar 31, 2011
Grant date	Oct 1, 2013
Priority date	—
Expiry date	Sep 21, 2031

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Multiple dies can be stacked in what are commonly referred to as three-dimensional modules (or “stacks”) with interconnections between the dies, resulting in an IC module with increased circuit component capacity. Such structures can result in lower parasitics for charge transport to different components throughout the various different layers. In some embodiments, the present invention provides efficient power distribution approaches for supplying power to components in the different layers. For example, voltage levels for global supply rails may be increased to reduce required current densities for a given power objective.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.