Semiconductor integrated circuit
US8547771B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 2, 2011 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Nov 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
To reduce power consumption of a semiconductor integrated circuit and to reduce delay of the operation in the semiconductor integrated circuit, a plurality of sequential circuits included in a storage circuit each include a transistor whose channel formation region is formed with an oxide semiconductor, and a capacitor whose one electrode is electrically connected to a node that is brought into a floating state when the transistor is turned off. By using an oxide semiconductor for the channel formation region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized. Thus, by turning off the transistor in a period during which power supply voltage is not supplied to the storage circuit, the potential in that period of the node to which one electrode of the capacitor is electrically connected can be kept constant or almost constant. Consequently, the above objects can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.