Area efficient arrangement of interface devices within an integrated circuit
US8549257B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2011 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Jan 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is disclosed that comprises: a core comprising logic circuitry: a plurality of interface devices for transmitting signals to and from the processing core, the plurality of interface devices comprising two types of interface devices: one type being a power interface device for delivering power to the core; and a second type being a signal interface device for transmitting data signals between the core and devices external to the integrated circuit; wherein the plurality of interface devices are arranged in two rows, an outer row towards an outer edge of the core and an inner row within the outer row closer to a centre of the core the inner row comprising one of the two types of interface devices and the outer row comprising an other of the two types of interface devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.