Method and apparatus for fine edge control on integrated circuit outputs
US8549342B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2011 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Jan 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more first memory cells and a second memory circuit also having two or more second memory cells. The first memory circuit may be configured to periodically sample the reference pulse at the rising edges of a first sample clock while the second memory circuit may be configured to periodically sample the reference pulse at the falling edges of the first sample clock. A combinatorial logic circuit may also be included to produce the output pulse having at least one adjusted edge based on a set of timing instructions and timing information provided by the first and/or second memory circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.