Memory device
US8549362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2012 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Sep 14, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first module calculates a failure occurrence risk index of each data storage area address. A second module calculates a power saving index of each data storage area address. A third module calculates an access speed index per unit data volume necessary to access each data storage area address. A fourth module generates a distribution table that represents the failure occurrence risk index, the power saving index, and the access speed index for each candidate address, with respect to data to be distributed. A fifth module selects a candidate address in the distribution table such that the power saving index and the access speed index meet restricting conditions and the failure occurrence risk index is minimized, and distributes the data to the candidate address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.