Verification apparatus
US8549451B2 · kind B2 · utility
2Cited by
1References
8Claims
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Key dates
| Filing date | Mar 2, 2010 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Apr 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design verification apparatus for a semiconductor device includes: a storage for storing layout information of the semiconductor device, the layout information including information of interconnection regions and a via regions; and a controller for dividing the interconnection regions into wire regions and cross regions, the cross regions corresponding to the via regions, respectively, the wire regions extending between the cross regions, respectively, and extracting at least one of the wire regions as a candidate having a potential risk of future disconnection defect on the basis of the length of the wire regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.