Method of manufacturing laminated wafer by high temperature laminating method
US8551862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2010 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Jan 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To provide a method of manufacturing a laminated wafer by which a strong coupling is achieved between wafers made of different materials having a large difference in thermal expansion coefficient without lowering a maximum heat treatment temperature as well as in which cracks or chips of the wafer does not occur. A method of manufacturing a laminated wafer 7 by forming a silicon film layer on a surface 4 of an insulating substrate 3 comprising the steps in the following order of: applying a surface activation treatment to both a surface 2 of a silicon wafer 1 or a silicon wafer 1 to which an oxide film is layered and a surface 4 of the insulating substrate 3 followed by laminating in an atmosphere of temperature exceeding 50° C. and lower than 300° C., applying a heat treatment to a laminated wafer 5 at a temperature of 200° C. to 350° C., and thinning the silicon wafer 1 by a combination of grinding, etching and polishing to form a silicon film layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.