Transistor structures and methods of fabrication thereof
US8552422B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Nov 2, 2012 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Nov 2, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/211
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An electronic device is presented, such as a thin film transistor. The device comprises a patterned electrically-conductive layer associated with an active element of the electronic device. The electrically-conductive layer has a pattern defining an array of spaced-apart electrically conductive regions. This technique allows for increasing an electric current through the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.