Semiconductor apparatus having reverse blocking characteristics and method of manufacturing the same

US8552471B2 · kind B2 · utility

Assignee

• NEC CORPORATION · JP

Inventors

• Yasuhiro Okamoto · Tokyo, JP
• Yuji Ando · Tokyo, JP
• Tatsuo Nakayama · Yokohama, JP
• Kazuki Ota · Tochigi, JP
• Takashi Inoue · Hachioji, JP
• Hironobu Miyamoto · Tokyo, JP
• Kazuomi Endo · Hiroshima, JP

Key dates

• Filing date: Dec 11, 2009
• Grant date: Oct 8, 2013
• Expiry date: Feb 26, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/513

Abstract

There is provided a semiconductor apparatus capable of achieving both a reverse blocking characteristic and a low on-resistance. The semiconductor apparatus includes a first semiconductor layer including a channel layer, a source electrode formed on the first semiconductor layer, a drain electrode formed at a distance from the source electrode on the first semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode on the first semiconductor layer. The drain electrode includes a first drain region where reverse current between the first semiconductor layer and the first drain region is blocked, and a second drain region formed at a greater distance from the gate electrode than the first drain region, where a resistance between the first semiconductor layer and the second drain region is lower than a resistance between the first semiconductor layer and the first drain region.