Single photon avalanche diodes
US8552482B2 · kind B2 · utility
2Cited by
1References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2012 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | May 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F30/225
Abstract
A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.