Semiconductor device and a method of manufacturing the same
US8552552B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2008 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Oct 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.