Method of measuring delay in an integrated circuit
US8552740B2 · kind B2 · utility
1Cited by
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26Claims
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Key dates
| Filing date | Dec 10, 2008 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Jan 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31725
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of measuring signal delay in a integrated circuit comprising applying a common clock signal at a circuit input and output, applying a test signal at the circuit input, detecting a corresponding output signal at the circuit output and detecting whether the test signal and output signal occur in a common part of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.