Method of testing reliability of semiconductor device
US8552754B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2011 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Apr 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2642
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The invention provides a method of testing reliability of a semiconductor device, wherein the semiconductor device has negative bias temperature instability NBTI. The method comprises steps of: measuring a NBTI curve of a first set of semiconductor devices; measuring 1/f noise power spectrum density and drain current at a predetermined frequency for the first set of the semiconductor devices, under a condition that the first set of the semiconductor devices are biased at a gate electric field; measuring an equivalent oxide thickness EOT of gate dielectric of the first set of the semiconductor devices; measuring 1/f noise power spectrum density and drain current at the predetermined frequency for a second set of semiconductor devices, under a condition that the second set of the semiconductor devices are biased at the gate electric field; measuring an EOT of gate dielectric of the second set of the semiconductor devices; and evaluating a degradation characteristic of the second set of the semiconductor devices by using the NBTI curve of a first set of the semiconductor devices. The method saves the time required for testing the reliability of a large numbers of semiconductor devices…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.