Programmable delay generator and cascaded interpolator
US8552783B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 10, 2011 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Nov 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00065
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable delay generator and a cascaded interpolator are provided. The programmable delay generator includes a first delay line and a second delay line, each having a respective plurality of stages of the same number. Each stage of the first line includes a respective delay buffer and has one signal input and one signal output. Each stage of the second line includes a respective selecting element and has two signal inputs, one select input for selecting one of the two signal inputs, and one signal output. The first line and the second line are configured in parallel, are interconnected, and have a same signal propagation direction. Each delay step provided by each stage of the second line is equal to a difference between a delay through one stage of the first line and a delay through one stage of the second line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.