Nonvolatile semiconductor memory device
US8553467B2 · kind B2 · utility
13Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2011 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Dec 29, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control circuit controls various kinds of operations on the memory cell array. The control circuit executes a pre-erase stress application operation in which, when an erase operation on one of the memory cells is executed, prior to the erase operation, a first voltage belonging in a certain voltage range is applied to the control gate while a second voltage having a value smaller than a value of the first voltage is applied to the channel region, whereby a stress is applied to the memory cell due to a potential difference between the first voltage and the second voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.