Performing stuck-at testing using multiple isolation circuits
US8553488B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2011 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Dec 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory may include a memory array, a plurality of control circuits, and a plurality of isolation circuits. The plurality of control circuits may be configured to generate control signals for the memory array. For example, the plurality of control circuits may include a plurality of word line driver circuits. The plurality of isolation circuits may be configured to receive the control signals from the plurality of control circuits and a plurality of isolation signals. A first isolation signal may correspond to the plurality of word line driver circuits and at least one second isolation signal may correspond to other ones of the plurality of control circuits. The first isolation signal and the second isolation signal may be independently controlled during memory tests to detect stuck-at faults associated with the plurality of isolation signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.