ADC clock selection based on determined maximum conversion rate
US8553748B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 2011 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Dec 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/0046
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present invention introduces a method, an apparatus and a computer program product for mitigating effects of alias responses in a transceiver, by selecting a clock rate for an analog-to-digital converter based on a determined maximum conversion rate of the ADC. The selected conversion rate places an alias response of the unwanted signal component to a frequency range which is substantially non-overlapping with a wanted signal component of the receiver. Furthermore, a temperature of the transceiver may be measured e.g. by a temperature compensation unit of a reference oscillator. Furthermore, a data table may be used by a processing unit for linking temperatures with maximum conversion rates of the analog-to-digital converter. The method is implemented in the processing unit of the transceiver which is further configured to execute the operations of the corresponding computer program product according to the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.