Memory power supply control circuit
US8555092B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 13, 2010 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Jan 30, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory power supply control circuit includes a number of memory slots, a platform controller hub (PCH), a first synchronous rectification driver, a number of second synchronous rectification drivers, and a complex programmable logic device (CPLD). The PCH is connected to the memory slots. The first synchronous rectification driver maintains a working state at all time. The CPLD is connected between the PCH and the second synchronous rectification drivers. The CPLD receives information from the PCH to determine a number of used memory slots, and controls the working states of the second synchronous rectification drivers according to the number of used memory slots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.