Pulse dynamic logic gates with LSSD scan functionality
US8555121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2011 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Dec 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318594
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scannable pulse dynamic logic gate may include an evaluation network that evaluates dynamic inputs in response to assertion of an evaluate pulse. The evaluate pulse may be generated from a clock signal such that it is shorter in duration than the clock signal. During a normal mode of operation, when the evaluate pulse is asserted, the evaluation network may discharge a dynamic node depending on the state of the dynamic inputs. The dynamic node may then drive output device(s). When the evaluate pulse is deasserted, the dynamic node may be precharged. The gate may also include scan input devices, which, during a scan mode of operation, may load scan input data onto the output node in response to assertion of a scan master clock. A storage element of the gate may receive and capture a value of the output node in response to assertion of a slave scan clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.